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FVanE1's avatar
FVanE1
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6 years ago

Why is the GTX clock output of the HPS running at 250 MHz?

We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. We do not route the GMII Tx data and GTX clock directly from FPGA logic to a PHY, but w...
FVanE1's avatar
FVanE1
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5 years ago

Hi,

I expected to find a pll_config.h file for the Arria 10, but what I can find in my buildroot software directories is:

./bsp/buildroot/output/build/uboot-tools-2018.03/board/altera/arria5-socdk/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/altera/cyclone5-socdk/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/aries/mcvevk/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/devboards/dbm-soc1/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/ebv/socrates/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/is1/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/samtec/vining_fpga/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/sr1500/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/terasic/de0-nano-soc/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/terasic/de1-soc/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/terasic/de10-nano/qts/pll_config.h

./bsp/buildroot/output/build/uboot-tools-2018.03/board/terasic/sockit/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/altera/arria5-socdk/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/altera/cyclone5-socdk/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/aries/mcvevk/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/devboards/dbm-soc1/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/ebv/socrates/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/is1/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/samtec/vining_fpga/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/sr1500/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/terasic/de0-nano-soc/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/terasic/de1-soc/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/terasic/de10-nano/qts/pll_config.h

./bsp/buildroot/output/build/host-uboot-tools-2018.03/board/terasic/sockit/qts/pll_config.h

Are you sure this is also working for Arria 10 devices? And how is the link made between Quartus and the pll_config.h file?

Best regards,

Frank