New Contributor
New ContributorHi,
If the GTX clock output would be 125 MHz instead of the measured 250 MHz, the data would be sent once. It looks like it is sent twice because of the doubled clock frequency. I measured the gtx clock frequency by incrementing a counter in my toplevel which runs at the GTX clock. The counter runs until 125000000 is reached, toggles an IO and starts counting again from zero. The IO signal is viewed with an oscilloscope which shows me a pulse train with a high time equal to the low time of 0.5 seconds. In other words, the counter must run at 250 MHz to count to 125000000 in 0.5 seconds.
I don't see wrong connections in the Platform Designer, I just export the GTX clock to FPGA user logic together with the GMII data and control signals (txd/rxd and txen/rxen).
Do I have to change to device tree when changing clock frequencies in Platform Designer?
Best regards,
Frank
Regular ContributorHi Frank,
I apologize for getting very late to you.
The answer is yes you need a to recompile the .dtb file, preloader image, etc. if there changes in the HPS and anything connected to it. This is so because the settings binaries need to be handoff correctly to take effect.
Have you tried recompiling everything to make sure the changes is taking place?
Regards.
