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FVanE1's avatar
FVanE1
Icon for New Contributor rankNew Contributor
6 years ago

Why is the GTX clock output of the HPS running at 250 MHz?

We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. We do not route the GMII Tx data and GTX clock directly from FPGA logic to a PHY, but w...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Frank,

I am still working to figure out this issue.

Firstly, can you double check that your design is connected correctly. Also, I could not find any information regarding data sent twice, which IP are you currently using and what is the clock frequency that you have set?