Forum Discussion
FVanE1
New Contributor
New ContributorWhy is the GTX clock output of the HPS running at 250 MHz?
We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. We do not route the GMII Tx data and GTX clock directly from FPGA logic to a PHY, but w...
EBERLAZARE_I_Intel
Regular Contributor
Regular Contributorhi Frank,
May I know which Quartus/SOC EDS version you are working on?
Also, did you have any error when compiling in Platform Designer/Qsys or in Quartus?
Regards.
FVanE1New Contributor
New ContributorI am using Quartus Pro 18.0.0. I can successful build an FPGA binary without having errors. We use buildroot to build all software stuff.
Best regards,
Frank
