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FVanE1's avatar
FVanE1
Icon for New Contributor rankNew Contributor
6 years ago

Why is the GTX clock output of the HPS running at 250 MHz?

We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. We do not route the GMII Tx data and GTX clock directly from FPGA logic to a PHY, but w...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

hi Frank,

May I know which Quartus/SOC EDS version you are working on?

Also, did you have any error when compiling in Platform Designer/Qsys or in Quartus?

Regards.

FVanE1's avatar
FVanE1
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6 years ago

I am using Quartus Pro 18.0.0. I can successful build an FPGA binary without having errors. We use buildroot to build all software stuff.

Best regards,

Frank