Why 390.625MHz clock to F-Tile Reference fequency

Hi,

I have the following two queries:

1. Is it possible to use separate oscillators (reference clock) to generate the reference clocks for the DDR5, HBM, SDM, HPS and NoC interfaces of the Agilex M FPGA, instead of deriving these clocks from the 390.625 MHz clock generated by the Si5518 PLL? Please confirm. 

    2.  Please find the attached screenshot from Section 4.4.2, "PTP Timestamp Accuracy," of the F-Tile Ethernet Hard IP User Guide. The guide states:

"Any 390.625 MHz frequency clock source can drive the TOD clock in 10GE mode."

Could you please confirm whether the 390.625 MHz clock generated by the Si5518 PLL and connected to the F-Tile reference clock pins is the clock source that drives the ToD clock when the F-Tile is operating in 10GE mode and for other ethernet modes this clock source is not used(required). 

Thank you for your assistance.