Hello, I am using Quartus Prime 18.1.0 Standard Edition and ModelSim - Intel Starter Edition 10.5b. I am trying to simulate an HPS design I made on Platform Designer. The macro file fails to load b...
Hi Anil,
I added the following line to the soc_system.do macro file I am using:
vlog -work work +incdir+/home/bmartinez/JT/c5FPGA/JtF31C8_c {/home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_common_axi.sv}
This inclusion required the following line to resolve “file not found” errors:
vlog -work work +incdir+/home/bmartinez/JT/c5FPGA/JtF31C8_c {/home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd}
The next error was for mgc_axi_bfm_pkg, I added the following line:
vlog -work work +incdir+/home/bmartinez/JT/c5FPGA/JtF31C8_c {/home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd}
As you can see, the missing package is written in VHDL. I next get the following errors:
# ** Error: (vlog-13036) /home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd(1): near "--": Operator only allowed in SystemVerilog.
# ** Error: (vlog-13069) /home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd(1): near "--": syntax error, unexpected --, expecting class.
# End time: 11:32:44 on Jun 17,2020, Elapsed time: 0:00:01
# Errors: 2, Warnings: 0
I need to research how to mix VHDL and Verilog for modelsim. I will add this task to my work queue.
Thanks for your help.
Ben
Occasional Contributor
