Forum Discussion
Jiayi_H_Intel
Occasional Contributor
Occasional ContributorWhen LVDS using external PLL, how does Rx recover data and deal with phase changing?
Hi experts, Question about LVDS implementation with external PLL. We are using 10M50 board. Since there is no LVDS tx output clock when using external PLL, how does Rx end recover the data it r...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
I understand your concern, with my know knowledge the explanation for the data realignment is not there in the lvdsUG for Max 10. And I do not have any procedure , but in Stratix 10 UG , there is recommendations. May be you can implement the same in Max 10.
Refer page no:27
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/archives/ug-s10-lvds-19-4.pdf?wapkw=phase%20recovery%20lvds
