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New ContributorWhen I m migrating from Arria II GX device to Arria V GZ FPGA I m facing these errors . Please suggest me how to go about it .
Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS clock tree(s))
Error (175001): Could not place 1 LVDS clock tree
Info (14596): Information about the failing component(s):
Info (175028): The LVDS clock tree name(s): IO_MISC:INST_IO_MISC|arriavgz_pll_lvds_output_inst~quadrant
Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between the LVDS clock tree and destination pin
Info (175027): Destination: pin iP48_RX_DIN[3]
Info (175015): The I/O pad iP48_RX_DIN[3] is constrained to the location PIN_E21 due to: User Location Constraints (PIN_E21)
Info (14709): The constrained I/O pad is contained within this pin
Error (175022): The LVDS clock tree could not be placed in any location to satisfy its connectivity requirements
Info (175021): The pin was placed in location pin containing PIN_E21
Info (175029): 3 locations affected
Info (175029): LVDS_CLK_TREE_X1_Y0_N1
Info (175029): LVDS_CLK_TREE_X1_Y88_N1
Info (175029): LVDS_CLK_TREE_X81_Y0_N0
Error (175006): Could not find path between the LVDS clock tree and destination pin
Info (175027): Destination: pin oS192_SFI_CLKOUT
Info (175015): The I/O pad oS192_SFI_CLKOUT is constrained to the location PIN_AF6 due to: User Location Constraints (PIN_AF6)
Info (14709): The constrained I/O pad is contained within this pin
Error (175022): The LVDS clock tree could not be placed in any location to satisfy its connectivity requirements
Info (175021): The pin was placed in location pin containing PIN_AF6
Info (175029): 1 location affected
Info (175029): LVDS_CLK_TREE_X81_Y88_N0
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Error (11802): Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 9 errors, 10 warnings
Error: Peak virtual memory: 2974 megabytes
Error: Processing ended: Wed Mar 13 01:29:39 2019
Error: Elapsed time: 00:05:46
Error: Total CPU time (on all processors): 00:05:44
Error (293001): Quartus II Flow was unsuccessful. 11 errors, 3489 warnings
5 Replies
a_x_h_75Contributor
It looks as though you have inappropriate constraints carried over from your original Arria II project. Remove all your old user constraints and then compile the design. Once you have the design compiled add pin and other constraints as necessary.
Cheers,
Alex
- SreekumarR_G_Intel
Frequent Contributor
Hello , Can you kindly let me know you still facing the same error ? Thank you , Regards, Sree
KRedd9Hi , Thanks a lot . you are correct there is old constraints .Presently I have commented those constraints and its running . Regards, Ramana
- SreekumarR_G_IntelHello, Thank you to Alex who answered your questions timely...Can you kindly close the thread? Regards, Sree
- KRedd9Yes. Alex suggestions helped me . I have closed the thread . Thank you. Regards, Ramana
