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ARey0's avatar
ARey0
Icon for New Contributor rankNew Contributor
6 years ago

What is the difference of stability between reference clock and output clocks in a PLL?

Hello In my project I need a frequency of 250 MHz and ±10ppm of stability as minimum, also I need two of this frequencies with 90 degrees between them. I have thought to use a PLL with a reference...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi @ARey0​

Lets take a datasheet for easy explanation: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-v/stx5_53001.pdf (Table 31).

For reference clock, the PLL need a stable reference clock. See tINCCJ. 250MHz vs 25Mhz has different sets of requirement.

For output clocks, refer to the the dedicated output clock spec, tOUTxxx

The PLL has been validated to behave as the spec, i.e. as long as you can provide the PLL with the tINCCJ, you can expect the tOUTxxx as specified.