What does "Hard Memory Controller" number mean?

Yes, you could potentially create up to 6 DDR4 memory interfaces though the interface widths would be limited by pin availability. Hard memory controllers are available in all the I/O banks of the device to provide flexibility for implementation. See this online training for an introduction to the memory interface architecture for these devices:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1121.html

#iwork4intel

Hi,

sstrell is correct.

In general, you can refer to below link to find out the support capability of each FPGA device

• https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support.html
• 1) device selection -> download EMIF device selector sheet

Thanks.

Regards,

dlim