We have our Cyclone10GX custom PCB, which is having cy10 interfaced to SFP module(1.25Gpbs Finisar) via its transceiver port. How to prove that the board is fine wrt Signal integrity.

Hello RGula,

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Best regards,

Crisselle C

Intel Customer Support

A Contingent Worker at Intel

Hi,

The main factor that will affect your board signal integrity from your Quartus design is the transceiver PHY PMA setting.

• As long as you are still using same PMA setting then the rest of design logic doesn't matter that much. (for instance, whether you add in MAC IP or not)
• However, if you change PMA setting then you would need to retest your board signal integrity again.

Typically we would advise to hit at least 95% BER confidence level to guarantee good signal integrity performance. However, this is just general guideline and different protocol may have its own spec to meet.

Feel free to checkout below BER confidence level calculator link

• https://www.jitterlabs.com/support/calculators/ber-confidence-level-calculator
• I have key in your test requirement and it's advisible to run test for around 40 minutes to meet 95% confidence level with zero BER. (refer to attached pic)

Thanks.

Regards,

dlim

Hi RGula can you share me (quartus project test) Cyclone 10GX interface SFP module. Thank! My mail is: [email protected]