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SYadl2's avatar
SYadl2
Icon for New Contributor rankNew Contributor
6 years ago

we are using Arria 10 SoC FPGA Development Kit Board. generated example design and trying to do Ethernet test (PHY Serial loopback). we are getting CRC errors

SYadl2's avatar
SYadl2
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Thank you for the immediate response.

we are using the reference design. the issue was clock settings were not done in clock controller GUI. after doing the correction we were able to get the packets without CRC errors

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Helo,

    Thank you for your prompt update, glad your issue is fix.

    If you have further question or any other question, we welcome you to file a new ticket.