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Honored Contributor
Honored Contributorwave form/vector file simulation is not matched with logic
hi i'm a student and i made a baseball count program.
it is really simple. just same as ball count. so i made a logic with karnaugh map. and i finished the coding. but simulation is not working correctly. i can't understand. what should i do for this? here is code. all the sub-modules are working well. please tell me the problom of this. :cry::(
module base9(iRST, iCLR, iCLK, iHIT, iSTRIKE, iBALL, iOUT, oSTRIKE, oBALL, oOUT);
input iRST, iCLR, iCLK, iHIT, iSTRIKE, iBALL, iOUT;
output oSTRIKE;
output oBALL;
output oOUT;
wire PGH, PGS, PGB, PGO;
//pulse generate part
P_GEN0 GEN1(iCLK, iRST, iHIT, PGH );
P_GEN1 GEN2(iCLK, iRST, iSTRIKE, PGS);
P_GEN2 GEN3(iCLK, iRST, iBALL, PGB);
P_GEN3 GEN4(iCLK, iRST, iOUT, PGO);
////////////////////////////LOGIC part
wire DA,DB,DC,DD,DE,DF,DG,SO,FB,tempOUT,TO,SC,BC;
//strike part
assign DA = ((~B)&PGS) | (A&(~PGS));
assign DB = ((A&(~B))&PGS) | (B&(~PGS));
assign SO = (B&PGS);
//ball part
assign DC = ((~C)&PGB) | (C&(~E)) | (E&(~PGB));
assign DD = (D&(~E)) | (E&(~PGB)) | ((C&(~E))&PGB);
assign DE = ((D&(~E))&PGB) | (E&(~PGB));
assign FB = (E&PGB);
//out condition
assign tempOUT = (PGO|SO);
//out part
assign DF = (F&(~tempOUT)) | ((~G)&tempOUT);
assign DG = (G&(~tempOUT)) | ((F&(~G))&tempOUT);
assign TO = (G&tempOUT);
//clear condition
assign SC = ~((PGO|FB)|PGH);
assign BC = ~((PGO|SO)|PGH);
//////////////////////DFF part
//strike part
D_FF Dd0 (SC, iCLK, DA, A);
D_FF0 Dd1 (SC, iCLK, DB, B);
//ball part
D_FF1 Dd2 (BC, iCLK, DC, C);
D_FF2 Dd3 (BC, iCLK, DD, D);
D_FF3 Dd4 (BC, iCLK, DE, E);
//out part
D_FF4 Dd5 (iRSTn, iCLK, DF, F);
D_FF5 Dd6 (iRSTn, iCLK, DG, G);
////////////////////output logic
assign oSTRIKE = {(~DA),(~DB)};
assign oBALL = {(~DC),(~DD),(~DE)};
assign oOUT = {(~DF),(~DG)};
endmodule
----------------------------------------------------------------------------------------
module P_GEN(iCLK,iRSTn,X,Y);
output Y;
input X,iCLK,iRSTn;
reg Y;
reg state ;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
always@(posedge iCLK, negedge iRSTn)
begin
if(~iRSTn) state <= S0;
else case (state)
S0 : if(X) state<=S1; else state<=S0;
S1 : if(X) state<=S2; else state<=S0;
S2 : if(X) state<=S2; else state<=S0;
endcase
end
always@ (state)
begin
case(state)
S1 : Y = 1'b1;
S0,S2 : Y = 1'b0;
endcase
end
endmodule
-------------------------------------------------------------
module D_FF(iCLK, iRSTn, D, D_out);
input iRSTn, iCLK, D;
output reg D_out;
always@(negedge iRSTn or posedge iCLK)
begin
if(~iRSTn)
D_out <= 0;
else
D_out <= D;
end
endmodule
