Forum Discussion
PShar30
New Contributor
5 years agoentity pmuga_01 is
port (
CLOCK_50 : in std_logic;
AUX_LEDO : out std_logic;
DAT_LED : out std_logic_vector(3 downto 0);
LED : out std_logic
);
end entity;
architecture Behavioral of pmuga_01 is
signal counter : integer := 0;
signal clk_1Hz : std_logic;
signal aux : std_logic;
signal data : std_logic_vector(3 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal output : std_logic_vector(3 downto 0);
signal wren : std_logic;
component pcycle
port(
address : in std_logic_vector(7 downto 0);
clock : in std_logic;
data : in std_logic_vector(3 downto 0);
wren : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end component;
begin
ram : pcycle
PORT MAP (
address => addr,
clock => clock_50,
data => data,
wren => wren,
q => output
);
process(CLOCK_50) is
begin
if rising_edge(CLOCK_50) then
if counter < 25000000 then
counter <= counter + 1;
else
clk_1Hz <= not clk_1Hz;
counter <= 0;
end if;
end if;
end process;
LED <= clk_1Hz;
AUX <= clk_1Hz;
process(AUX) is
begin
if clk_1Hz = '1' then
AUX_LEDO <= '0';
wren <= '1';
data <= "1111"; -- data 1111 is stored in addr 00000000
addr <= "00000000";
else
AUX_LEDO <= '1';
wren <= '0';
addr <= "00000000";
DAT_LED <= output;
above VHDL code used to store data in ram which I created using ip integrator...
from mmap import mmap
MAPSIZE = 10
offset_mem = 0xFFFF0000
with open("/dev/mem", "r+b") as f:
mem = mmap(f.fileno(), MAPSIZE, offset=offset_mem)
packed_reg = mem[:]
print(packed_reg.encode('hex'))
this python code is used to collect data using python. i get address of on chip memory as 0xFFFF0000 from this link. https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#topic/sfo1410068453374.html
but the output of python doesn't shows the correct data. at positio 0xFFFF0000