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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL:apcial_altera_wdr

hi,friend!

it is VHDL, I can not understand the ext(a,b).

example:

constant active_width : integer := 16;

constant offset_shift : integer := 16;

wr_offset <= ext((active_width+1) & offset_shift, wr_offset'length);

what is the mean? :oops:

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It doesnt mean anything, because you cannot use ext on integers (and you cant use & on them either)

    ext is part of the std_logic_arith package to add extra bits to std_logic_vectors.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    oh thank you !

    but it is used in demo of altera 's project ,(apcial_altera_wdr).

    I want to change VHDL to verilog ,because I can not use VHDL do anything.but verilog is easily.

    if:

    active_wide std_logic_vendor (3 downto 0)

    offset_**** std_logic_vendor(3 downto 0)

    wr_offset std_logic_vend(7 downto 0)

    wr_offset <= (active_wide + 1) & offset_****;

    it is OK ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    thats better, but only if you include std_logic_unsigned or std_logic_signed packages, which are not standard packages.