Honored Contributorhi,friend!
it is VHDL, I can not understand the ext(a,b). example: constant active_width : integer := 16; constant offset_shift : integer := 16; wr_offset <= ext((active_width+1) & offset_shift, wr_offset'length); what is the mean? :oops:
Honored ContributorIt doesnt mean anything, because you cannot use ext on integers (and you cant use & on them either)
ext is part of the std_logic_arith package to add extra bits to std_logic_vectors.Honored Contributoroh thank you !
but it is used in demo of altera 's project ,(apcial_altera_wdr). I want to change VHDL to verilog ,because I can not use VHDL do anything.but verilog is easily. if: active_wide std_logic_vendor (3 downto 0) offset_**** std_logic_vendor(3 downto 0) wr_offset std_logic_vend(7 downto 0) wr_offset <= (active_wide + 1) & offset_****; it is OK ?Honored Contributorthats better, but only if you include std_logic_unsigned or std_logic_signed packages, which are not standard packages.
Honored ContributorOH,thank you !!
