VHDL:apcial_altera_wdr

oh thank you !

but it is used in demo of altera 's project ,(apcial_altera_wdr).

I want to change VHDL to verilog ,because I can not use VHDL do anything.but verilog is easily.

if:

active_wide std_logic_vendor (3 downto 0)

offset_**** std_logic_vendor(3 downto 0)

wr_offset std_logic_vend(7 downto 0)

wr_offset <= (active_wide + 1) & offset_****;

it is OK ?