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It seems to me, that some confusion is still present in this discussion, although a lot has been clarified.
The confusion was obvious to me, as you mentioned the SMA connectors. I don't have a board documentation except a photo, but I wouldn't expect any SMA connector wired to a general purpose IO pin at this board. Very clearly, 24 are connected to GX transceivers. The remaining most likely interface clock in- or outputs.
GX transceivers can't be used as regular serial (LVDS) interfaces. Apart from the said minimum bit rate of 600 MBPSs (that may be handled by oversampling), they require DC balanced (8b10b encoded) bit streams, cause they are AC coupled.
So the answer to your original question
using stratix ii gx transceiver on low data rate is no, you can't (except for some special cases). And the said board most likely has no other connected IO pins suitable for this purpose.
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I just do not understand this.
Please imagine this with me.
What if all what I want the fpga to do is output the same clock that I am inputting.
Just a simple verilog program to assign an output to be the same as the clock.
if my clock is around 50MHz, wont the output operate at 50MHz too? (50Mbps)?
I just do not understand how this (600Mbps as minimum) works! I just need the board to do me this simple task i mentioned above.
Please clearify this for me.
Honored Contributor
