Using HPS_KEY and HPS_LED in FPGA via LOAN IO in DE1-SoC

Hi,

I am using DE1-SoC with Quartus II v13.1 and v14.0.

I want to use GPIO attached to HPS from the FPGA side.

I referred to some related documents and forum topics:

how can i implement hps loan io and confirm timing? (http://www.altera.com/support/kdb/solutions/rd04132014_234.html)

an 702: interfacing a usb phy to the hard processor system usb 2.0 otg controller (http://www.altera.com/literature/an/an702.pdf)

instantiating the hps component (http://www.altera.com/literature/hb/arria-v/av_54027.pdf#page=10)

accessing hps pins (http://www.alteraforum.com/forum/showthread.php?t=41652)

how to let fpga get access to hps pins (http://www.alteraforum.com/forum/showthread.php?t=44486)

Then I added some LOAN IO code to GHRD source.

Its main part is as follows and the exact code is attached.

assign loan_io_oe = 1'b1; // HPS_LED is in output mode
assign loan_io_out = loan_io_in; // HPS_LED <- HPS_KEY
assign LEDR = loan_io_in; // LEDR <- HPS_KEY

Now my FPGA can access an input pin (HPS_KEY) attached to HPS.

However, it can not access an output pin (HPS_LED).

When I program the FPGA, LEDR[0] turns on and HPS_LED is off.

Pushing the HPS_KEY turns LEDR[0] off, but HPS_LED keeps off.

HPS_LED is not broken as I tested using hps_gpio Demo project.

I also tested both 1 and 0 of USER_IO_DIR bit for HPS_LED,

which controls HPS GPIO direction.

My question is how I can control LOAN IO as an output pin.

What I exactly did is:

* Copy de1_soc_GHRD project in V.1.2.0 SystemCD as a new project.

* Double click hps_0 in Qsys.

* Disable GPIO53/54 buttons and enable LOANIO53/54 buttons in Periferals Mux Table in Periferal Pins tab.

* Export h2f_loan_io as hps_0_h2f_loan_io.

* Perform Generate HDL and Finish.

* Modify ghrd_top.v as attached patch.

* Start "Analysis & Synthesis".

* Assign 3.3-V LVTTL to LOANIO53/54 pins in Pin Planner.

* Start Compilation.

Thank you very much and Regards,