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Altera_Forum's avatar
Altera_Forum
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13 years ago

Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

Hi, Forgive me if the question is basic. I am new to the field of FPGAs. I give a short version of the question. And a long version of the question. For those interested :). Note: Re...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I believe he meant that aligning samples from the ADC could pose a problem with transceivers.

If your requirement is such that samples from each channel of the ADC have to be in sync, then it might pose a problem knowing which sample was which.

This shouldn't be much of a problem if there are only 3 ADC channels. The case I was discussing had 96 channels :)

Although, only he can properly answer your question. This was my understanding of it.

I guess it would also depend on the ADC in question.. Which part are you using?

Hope this helps.

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Zubair