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Altera_Forum
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13 years ago

Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

Hi, Forgive me if the question is basic. I am new to the field of FPGAs. I give a short version of the question. And a long version of the question. For those interested :). Note: Re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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My advice would be to steer clear of the transceiver channels for ADC interfacing. However, you could consider them as communications interfaces for transferring ADC data between boards. For example, ADC-to-DE3 interface via LVDS, and then DE3-to-Stratix V data transport using transceivers (and possibly Stratix V to Stratix V transport via transceivers if needed).

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Hi Dave,

I stumbled upon this thread as I'm currently working on a project using a Stratix IV GX device for the first time (EP4SGX70HF35) while interfacing with 16-bit ADCs. My dilemma right now is trying to figure out the best way to get the data into the FPGA. What's the main reason you advised staying away from the transceivers when interfacing with the ADCs? If I am using the transceivers, do I need to use the ALTGX megafunction in order to get data in/out or can I treat them like regular I/O pins?

Thanks. You seem quite knowledgeable.

-Mike