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Altera_Forum
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13 years ago

Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

Hi, Forgive me if the question is basic. I am new to the field of FPGAs. I give a short version of the question. And a long version of the question. For those interested :). Note: Re...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You are correct and we did think of such a design during our brainstorming sessions. i.e. adding a smaller fpga on the ADC front-end card to serialize the channels.

However..

The DE3 setup already exists. Along with a version of the custom ADC Front-end daughter cards.

Currently, we are upgrading the capability of the entire setup by adding a Stratix V behind 2 DE3s.

Hopefully, in the next iteration, we'll have ADC's with the JEDEC standard. And we'll be able to directly connect a lot of ADCs with one FPGA kit.

Indeed, that would simplify stuff a lot :).

Thanks,

Zubair