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We intend on using the AFE5807 by TI, 8 Channel, 12bit, 80MSps, specifically for Ultrasound applications.
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From a brief look at the data sheet, each 12-bit channel is multiplexed onto 2 LVDS signals. At a sample rate of 80MSps, the LVDS lane rate is 480Mbps. This is "slow" enough that you could interface each ADC to a Cyclone IV GX device, and use that to serialize to a much higher data rate on a transceiver, eg., each 8 channel ADC requires 16 x 480Mbps LVDS inputs for a total data rate of 7680Mbps, 8/10B encoded this would be 9600Mbps, which could be divided across four transceiver lanes at 2400Mbps or two at 4800Mbps (on an Arria device). The EP4CGX22 has 4 transceiver lanes and 17 LVDS in the smallest package, 52 in the larger package. The four output lanes can be transmitted over QSFP (or QSFP+) cables. Alternatively, you could use an Arria or Stratix series device and use a faster lane rate. The faster lane rate would allow more channels to be routed to your high-end processing node.
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And there are 18 ADCs in total. (18 x 8 = 144 Channels) ;)
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Lets say each ADC was converted to a 9.6Gbps data stream ... then you only need 18 10Gbps transceiver channels to get all ADC data into a single FPGA.
I know its 'easier' to use kits than to develop your own boards. However, you might find it easier to develop a front-end board for your ADC board that then allows you to interface to your Stratix V kit (or some other kit). For example, getting all ADC data into a single FPGA may save significant development time elsewhere in the project, eg., if it eliminates trying to figure out how to distribute processing over multiple boards. If your ADC front-end board re-transmits ADC data in a format similar to JESD204, then future upgrades of the ADC will also be simpler, since the interface to the processing node will not change.
Feel free to continue discussing this design on the forum, or just email me directly (via my forum name), if you like.
Cheers,
Dave
Honored Contributor
