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Altera_Forum
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15 years ago

USB programmer

Hello everyone,

I want to design a low cost development board for the Altera Max CPLD's. I plan to do the programming through a USB port as the parallel and the serial ports are not available on most of the computers.

Does anyone have a schematic to program the Altera Max CPLD's though USB? It would be of great help to me.

Thanks and Regards,

Max

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    MaxII CPLDs are programmed via JTAG

    what you request are the schematics of the usb blaster, and the logic inside the pld between the USB chip (FTDI 245 for example) and the JTAG IF that goes to your target..

    The source for the pld will be a problem due to copyrights
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi MSchmitt,

    From what I know, the JTAG protocol used for programming is not disclosed by Xilinx, whereas Altera has.

    I have even found a circuit schematic for the Altera CPLDs, but it involves using another CPLD for the firmware part. I was wondering whether a simpler soultion exists where just an intermediate chip like FT232/245 would serve the purpose. After all, even JTAG uses very few pins.

    Is it possible to develop the programmer by means of only one intermediate programming IC?

    Thanks and Regards,

    Max
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Max,

    You may find it easier to grab yourself a USB<->parallel converter and use the ByteBlaster. I haven't tried it myself, so I don't know if it will work, but I do know that you'll have difficulty getting Altera to reveal what's on that CPLD.

    Regards,

    -slacker
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    See this discussion:

    http://www.edaboard.com/viewtopic.php?t=114946&start=0&sid=a0a224571f1ee79470ea7fd2cdb6dbd2

    Just keep the same USB chip (FT245BL) to maintain driver compatability with Altera Blaster products. Also you'll need to flash correct PID/VID into the EEPROM so that the correct driver is used. Then load up the CPLD with the code that does the serial<->parallel conversions.

    You can find schematics online that show how the chips are physically connected, however Altera does not provide the CPLD logic. There exists some open source logic that functions similarly though.