Unwanted frequency shift in DA-converted signal

Thank you for your replies.

I wasn't aware of a method DDS. The problem is that my project is a little bit more complex. I need the same signal on two analog channels going through a resonator circuit. The will be a different delay on these two lines so I have to sync the signals afterwards in the FPGA. So I need to send a sync signal at the beginning.

A part of my code for the signal generation:

F_sample = 125e+6;    %Which is also my FPGA clock (125 MHz)
samples = 8192;
%Generate Source Signals
steps = 0:(samples-1);
for index = 1:number_of_resonators
    Omega = 2*pi*frequency_vector(index)/F_sample;
    s(index,:) = amplitude_per_resonator*sin(Omega*steps);
    signal_source = signal_source + s(index,:);
end
%Add Sync Peaks:
signal_source(1,11:(length(s(1,:))+10)) = signal_source(1,:);
signal_source(1,1:5) = (samples-1);
signal_source(1,6:10) = 0;

The frequency_vector contains the frequencies, e.g. 10, 20 and 30 Mhz. This digital signal is stored in a LUT on FPGA. My LUT is 8192 values long and addressed via a counter.

During measurement the data is AD-converted and stored in RAM. Then I calculate the synced signal via the sync peak (see code) to avoid phase difference on the channels. Then this data is further processed.

The frequency shift also occurs without the sync peak at the beginning. The Signal/Spectrum Analysers have a resolution in the lower Hz-range. There is no limitation here.

I might try a simple DDS design now but it would be awesome to continue to use my LUT method as it is very adaptive and simple to handle.

Thanks again!