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RGoem's avatar
RGoem
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6 years ago

Undefined pin state prior to loading rbf

Hello everyone,

I'm using a de0-nano-soc development board which has a Cyclone V including a HPS. I'm running U-Boot to load an rbf file at boot and then linux is ran. However when powering on the board it seems the FPGA is not doing anything prior to loading the rbf. This is a problem for me because the output pins I'm using are in a bad state sometimes. One pin is used to control a power hungry backlight and when the pin is high the backlight will be on full throttle. The power supply can't handle this spike and thus the board will reboot.

Is there a way to assign a default state to a pin or instruct the FPGA to start running the code before u-boot loads a new rbf image?

5 Replies

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hello.

    FPGA is empty before rbf configuration by uboot. You cannot run anything on FPGA before Uboot.

    Let me check with my internal team and let you know if I could get a feedback.

    Thanks

  • FawazJ_Altera's avatar
    FawazJ_Altera
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    6 years ago

    Is this pin related to FPGA I/O or HPS I/O ?

    If it is HPS I/O, it is no effected by FPGA configuration. This happens after executing Preloader which configures HPS I/O pin settings such as weak-pullup or drive strength. these settings comes from Quartus when you generate the files, which might not be controlled by customer.

    If it is FPGA I/O pin, I need to check with configuration engineer regarding this .

    Thanks

    • RGoem's avatar
      RGoem
      Icon for New Contributor rankNew Contributor
      6 years ago

      Thank you for your response!

      It is regarding the FPGA I/O pins.

    • RGoem's avatar
      RGoem
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      6 years ago

      Dear Fjuumaah,

      Is there any update on this?

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hello,

    it seems there is a limitation here.

    The uboot will freeze all the pins, configure the FPGA, then unfreeze and apply the pins settings. Before that, there is no function that can be done on FPGA.

    Arria 10 SoC might support your need, since you can let uboot configure the pins before configuring the FPGA.

    Thanks