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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Unable to merge three 9x9 multipliers into a single DSP

In cyclone V devices each DSP device will have three 9x9 multipliers as given in the below document (page 3-10) ​ https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I believe you might be aware of it. Just would like to share with you that you can also make use of the existing DSP feature multiplier HDL templates in Quartus to ease your coding. For example, in the workaround that I previously discuss, you may refer to the Insert Template -> Verilog HDL -> Full Designs -> Arithmetic -> DSP Features -> DSP Features for 28-nm Device -> "Multiplier with One Operand from Pre-Adder" for example code. You may set input C = 0x1 to leverage the pre-adder. Hopefully this will be helpful.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin