Yogesh
Occasional Contributor
5 years agoUnable to merge three 9x9 multipliers into a single DSP
In cyclone V devices each DSP device will have three 9x9 multipliers as given in the below document (page 3-10)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
I am unable to merge three 9x9 from a single DSP. If I use three lpm_mult (each performing 8x8 multiplication ), quartus fitter will use 3 separate DSPs instead of a single DSP.
Consider three 8x8 multiplications :
A1[7:0] x B1 [7:0] = out[15:0] -->first 9x9
A2[7:0] x B2[7:0] = out2[15:0] -->second 9x9
A3[7:0] x B3 [7:0] = out3[15:0] -->third 9x9
I want to implement above 3 lines using a single DSP(with latency of 3 clock cycles).
Please provide me a simple code/example design to do so.
thankyou
Regards
Yogesh