Unable to detect 100Hz input signal properly
Hi,
We are using cyclone10lp in one of our design.
In that design, we are trying to take a 100Hz clock input and use it for some application but as soon as it enters FPGA the signal is getting random intermediate logic highs and lows. Able to observe these random level changes in signal tap as well.
100Hz signal is connected to DIFFIO_R45P pin.
Input signal is clean and no such spikes are present in the clock.
My main input clock is 25MHz and it is given to CLKUSR pin.
As an experiment, have tried to take this 100Hz clock in and assign to a different pin as output and see the wave through CRO, i am seeing many voltage spikes during transition of 100Hz clock from high to low or low to high.
Note sure why FPGA is unable to detect this 100Hz clock properly, please suggest what i can do to detect the 100Hz input clock properly.
Thanks & Regards,
Harsha.