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Harsha4's avatar
Harsha4
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1 year ago

Unable to detect 100Hz input signal properly

Hi, We are using cyclone10lp in one of our design. In that design, we are trying to take a 100Hz clock input and use it for some application but as soon as it enters FPGA the signal is getting rand...
Fpga Devkit
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
sounds like the 100 Hz signal has low dV/dt (slow edges), in this case seeing multiple transitions per edge is just expectable. FPGA requires digital signals with fast edges, e.g. < 1 ns tr/tf if edges matter. Did you try to enable schmitt-trigger for the respective input?

Regards
Frank