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RK's avatar
RK
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7 years ago

unable to debug uboot in arria10 soc

Hello We tried using board design example available "A10_FPGA_to_HPS_Bridge_Design_Example" from "https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/soc/f...
FawazJ_Altera's avatar
FawazJ_Altera
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7 years ago
Hello, Would you please share with me the steps you followed to create the application? Thanks
PZhan12's avatar
PZhan12
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7 years ago

Hello,

I have a similar problem in ​debugging uboot in arria10 soc. When I connect my Uboot debug to the SoC Target, I got this:

Error(CMD16-TAD59-NAL18):

Error(CMD16-TAD59-NAL18):
 
! Failed to load "u-boot"
 
! Download of 149,528 bytes to address S:0xFFE00000 failed while writing block of 4,096 bytes to address S:0xFFE00000
 
!Bus error on memory operation.

The .ds file I use is generated automatically by BSP Editor:

​

############################################################
 
#
 
# Copyright Altera 2015
 
# All Rights Reserved
 
# File: uboot.ds
 
#
 
############################################################
 
 
 
#
 
# stop processor if running
 
# and then reset processor
 
#
 
stop
 
wait 5s
 
reset system
 
stop
 
wait 5s
 
 
 
set trust-ro-sections-for-opcodes off
 
 
 
# Load uboot elf
 
loadfile $sdir/uboot-socfpga/u-boot 0x0
 
start
 
wait
 
 
 
restore $sdir/devicetree.dtb binary &_end
 
 
 
#
 
# set a breakpoint on board_init function
 
#
 
tbreak board_init
 
 
 
# tell target to continue executing
 
continue
 
 
 
# wait for breakpoint
 
wait 60s

Best wishes.

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hello,

    It looks like the debugger cannot talk to the board. Typically this happens because board is not in a good state – most commonly because Linux is already running there. I suggest to do the following things:

    1. Try to remove the SD card in case it tries to boot to Linux.
    2. Try to run the commands from the script manually one by one and see what happens.
    3. Try to reduce JTAG clock speed.

    For reference, typically running A10 U-Boot through debugger goes like this:

    • U-Boot is configured with external FPGA configuration from bsp-editor
    • FPGA is configured with quartus programmer
    • U-Boot is then downloaded and ran through the DS-5 debugger like you did

    Thanks