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Parisa's avatar
Parisa
Icon for New Contributor rankNew Contributor
5 years ago

unable to create symbol file for current file (Verilog HDL file) in Quartus prime pro 20.3

Hi everyone, I am working on Quartus prime pro 20.3 and I was going through "my first fpga tutorial". Here it says after creating simple_counter.v verilog code, we need to go to create/update and c...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.