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Parisa's avatar
Parisa
Icon for New Contributor rankNew Contributor
5 years ago

unable to create symbol file for current file (Verilog HDL file) in Quartus prime pro 20.3

Hi everyone, I am working on Quartus prime pro 20.3 and I was going through "my first fpga tutorial". Here it says after creating simple_counter.v verilog code, we need to go to create/update and c...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Parisa,


This this option has been removed from the Intel® Quartus® Prime Pro Edition software starting version 18.0 and only available in Standard Edition. The reason is because symbol files are not an industry standard format. Below is KDB related to your issue.


https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2018/why-is-the--create-symbol-files-for-current-file--option-not-ava.html


Thanks,

Regards