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srimathi's avatar
srimathi
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1 year ago

UART functionality in altera max II EMP240 CPLD

Hi everyone, I'm currently working on implementing UART communication on an Altera MAX II CPLD using Verilog. As I'm still learning, I would really appreciate it if anyone could share UART transmitt...
Fpga Devkit
FvM's avatar
FvM
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1 year ago

Hi,
compiling the Verilog uart code, I see multiple drivers for baud_counter in uart_rx module. Can be fixed by merging Baud rate counter and UART receiver state machine always blocks.

Regards
Frank

srimathi's avatar
srimathi
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1 year ago

Hi,

Is that code is working for you, I barely see any waveform on the tx line.