Type error near ; current type std_logic_vector; expected type std_ulogic error in vhdl. How to solve this error

Can you post your code?

#iwork4intel

Hi Sisira,

The error may be due to a mismatch in vector size or operator misinterpretation.

Share your code.

Regards

Anand

This is my code

Library ieee;

Use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity ttcaam is

port(clk:in std_logic);

end ttcaam;

architecture Behavioral of ttcaam is

type mem0 is array(0 to 5) of std_logic_vector(0 to 5);

signal mem:mem0;

type mem1 is array (0 to 5) of std_logic_vector(0 to 5);

signal mem_1:mem1;

type mem2 is array (0 to 5) of std_logic_vector(0 to 5);

signal mem_2:mem2;

type mem3 is array (0 to 5) of std_logic_vector(0 to 5);

signal mem_3:mem3;

type mem4 is array (0 to 5) of std_logic_vector(0 to 5);

signal mem_4:mem4;

signal q1:std_logic_vector(0 to 5);

signal q2:std_logic_vector(0 to 5);

signal q3:std_logic_vector(0 to 5);

signal q4:std_logic_vector(0 to 5);

signal q5:std_logic_vector(0 to 5);

signal q6:std_logic_vector(0 to 5);

constant r:std_logic_vector(0 to 1):="00";

constant s:std_logic_vector(0 to 1):="01";

constant t:std_logic_vector(0 to 1):="10";

constant u:std_logic_vector(0 to 1):="11";

constant v:std_logic_vector(0 to 1):="-0";

constant w:std_logic_vector(0 to 1):="-1";

constant y:std_logic_vector(0 to 1):="0-";

constant z:std_logic_vector(0 to 1):="1-";

signal q:std_logic_vector(0 to 5);

signal i:integer ;

signal j:integer:=0;

signal a:integer;

signal b:integer;

signal c:integer;

signal d:integer;

signal e:integer;

begin

q1<="001001";

q2<="11-100";

q3<="-10010";

q4<="100-11";

q5<="0-01-1";

q6<="-10001";

process(clk,q(1),q(3))

begin

if(i=0) then

mem(i)<=q1;

i<=i+1;

elsif(i=1) then

mem(i)<=q2;

i<=i+1;

elsif(i=2) then

mem(i)<=q3;

i<=i+1;

elsif(i=3) then

mem(i)<=q4;

i<=i+1;

elsif(i=4) then

mem(i)<=q5;

i<=i+1;

elsif(i=5) then

mem(i)<=q6;

i<=i+1;

else

if(j<=5) then

q<=mem(j);

case q(1) and q(3) is

when r=>

e<=e+1;

mem_1(a)<=q;

a<=a+1;

when s=>

e<=e+1;

mem_2(b)<=q;

b<=b+1;

when t=>

e<=e+1;

mem_3(c)<=q;

c<=c+1;

when u=>

e<=e+1;

mem_4(d)<=q;

d<=d+1;

when v=>

mem_1(a)<=q;

a<=a+1;

mem_3(c)<=(q(0),'1',q(2),q(3),q(4),q(5));

c<=c+1;

when w=>

mem_2(b)<=(q(0),'0',q(2),q(3),q(4),q(5));

b<=b+1;

mem_4(d)<=(q(0),'1',q(2),q(3),q(4),q(5));

d<=d+1;

when y=>

mem_1(a)<=(q(0),q(1),q(2),'0',q(4),q(5));

a<=a+1;

mem_2(b)<=(q(0),q(1),q(2),'1',q(4),q(5));

b<=b+1;

when z=>

mem_3(c)<=(q(0),q(1),q(2),'0',q(4),q(5));

c<=c+1;

mem_4(d)<=(q(0),q(1),q(2),'1',q(4),q(5));

d<=d+1;

end case;

j<=j+1;

end if;

end if;

end process;

end;

Without line numbers or a fixed width font, it's a little tricky to figure out what's going on here, but I do see an errant space:

signal i:integer ;

I don't know if that's the issue. Does the tool say which line number(s) have issues?

#iwork4intel

Hi Sisira,

1. At line 85, you have used the logical operator "and" which is defined for BIT and BOOLEAN types.
2. At 86 you are expecting 2bits for state "r"

VHDL concatenate operator is an ampersand (&). It can be used to combine two or more items together.

Example pad 0 in MSB.

case( 0 & (q(1) and q(3)) is

or case(q(1) & q(3)) is

Regards

Anand

Okay,

Add below lines at the appropriate location and check

signal x:std_logic_vector(0 to 1);

x<=q(1)&q(3);

case (x) is

when others =>

Regards

Anand