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Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Two CV GT Dev Kits talking to each other as RP and EP?

Dear community,

I have two CV GT Dev Kits and would like them to communicate with each other as Root Port and Endpoint.

Means that the FPGA on one board is configured as the Root Port and the FPGA on the other board is configured as the endpoint, as shown in this example (chapter 16).


I want to plug the two cards into a PCIe bus board similar to this one.

What do you think, will this work?

Best regards

4 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    If you are familiar with pcie and dma transaction it isn't difficult task.

    All fpga should know address of each other.

    Then start transfer based on A/B fpga address instead of host address.

    But you should carefully select appropriate host pc: pc with integrated pcie switch will be better option,

    in any case check before buying.


    Technically, you can connect FPGA's anyway you want. SPI, I2C, PCI, PCI Express, LVDS, DDR, etc.

    My guess is it will be as simple as possible, whereby you connect as many wires as you physically can, depending on how much data you'll be sending, and then just send one bit of data per clock, assuming the clock speed is slow enough and there is a relationship between the clocks on the two FPGAs.


    Hope this clarified


    Regards,

    Wei Chuan


    • Zarquin's avatar
      Zarquin
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hi Wei Chuan,

      thank you very much for your prompt reply.

      "But you should carefully select appropriate host pc: pc with integrated pcie ..."

      There will be no host PC.

      The project is now working with a 5CSXC6N development board as a Root Port in whose PCIe slot one of the above mentioned CV GT Dev Kits is inserted. But the SOC part of the 5CSXC6N isn't used - only the advanced qsys from the example.
      The app on the 5CSXC6N does the job of the OS and configures the Avalon-ST HIPs as root port (5CSX6N) and as Endpoint (5CGTD9). The communication between the two FPGAs works.

      But in the future only 5CGTD9 FPGAs will be used. That's why I need to know whether the tasks that the 5CSXC6N now performs could in principle also be taken over by a second 5CGTD9.

      A PCIe switch is planned for later, but it will take some time until a suitable board has been developed. In the meantime, I wanted to make an attempt with the above constellation (plug the two CV GT Dev Kits into a ready-to-buy PCIe bus board).

      Will this (without host pc) still be "as simple as possible" or is there something else I have to consider?

      Best regards

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        Hi,

        The Intel Cyclone V FPGA card are Endpoint or Rootport-Support.
        For the second device, I not use it before. I suggest you to ask the related manufacturer for detail information or shall leave this to the community user to help to answer.

        As long as the communication is work by right it shall be no problem.

        Let me know if you have any other concerns.

        Regards,

        Wincent_Intel

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi

    Thanks for accepting the answer, hence this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel