Honored Contributor
Honored ContributorHi Bob,
I used myself that example design as starting point for another altera dev kit that I had In attachment you can find my design: I used 13.1 without any problem. I suggest you to check your Qsys connections as suggested in the wiki in particular that you connected the Jtag to avalon master port to the reconfiguration controller slave one. If they are fine, verify that you're not keeping all in reset and that the clocks of your system are present at FPGA pins and at right frequency. Anyway maybe a screenshot of what you've to do inside TTK could help. This is what happen to me in step 5 you're referring to: http://www.alteraforum.com/forum/attachment.php?attachmentid=10591&stc=1 Once you do that you can go under control receiver and start your tests to see that you've no error (or adjust equalization parameters if needed) http://www.alteraforum.com/forum/attachment.php?attachmentid=10592&stc=1 or also run the EyeQ to see the eye opening (in my case as you can see it is pretty open) http://www.alteraforum.com/forum/attachment.php?attachmentid=10593&stc=1 Last but not least you can check from QII the logical xcvrs name and physical pin used that you assigned previously in your compilation. http://www.alteraforum.com/forum/attachment.php?attachmentid=10594&stc=1 I attach you here my design, but as said it is not for the same board so I changed pinout and also some clocks if I remember correct (it was more than 1 year ago). I hope it helps Cheers
