TSE MAC and Marvell 88E1111

Thank you for this snapshot !!!

Worth 1000 words.

Hello,

I read this discussion but i have question:

have you somebody uClinux running on StratixIII DSP kit with TSE Marvell 88E1111 ethernet chip ?

Everything looks ok, but don´t work ...

When i use the

/>ifconfig eth0 hw ether 00:07:ed:ff:4a:d7

/>ifconfig eth0 192.168.1.234

/>ifconfig eth0 up

/>route add default gw 192.168.1.254

linux report - Trying 10/HALF - in this moment i don`t know what it does ?

After this i try ping to ip of my pc, it finish by request timeout (and tx led on board don`t blink).

I haven`t problem with reset i think, because examples of webserver (on uC-OSII) work fine and simple socket server too.

Where could be mistake ?

Thank you very much.

Jan Naceradsky, Czech Reublic

Hello to everybody.

I'am using cyclone III dev kit, marvell 88e1111 PHY, Triple Speed Ethernet and nios II.

i want to initialize PHY.

i try to write code for initializing, but i don't know how to address PHY through the MDIO.

in tse_regs.h there is

IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num)

IORD_16DIRECT(base, 0x200 + (mdio * 0x80) + (reg_num * sizeof(alt_u32)) )

i think i can use it, but what are the parameters?

base - tse_mac_base?

mdio - The MDIO address of the PHY device is configured to the value 18 (0x12)?

The TSE is able to communicate with up to two PHYs through MDIO. You need first to set up the MDIO address of the PHY, with one of those calls:

IOWR_ALTERA_TSEMAC_MDIO_ADDR0(base,data)
IOWR_ALTERA_TSEMAC_MDIO_ADDR1(base,data)

Obviously the first line sets the MDIO address for the PHY number 0 and the second one sets the MDIO address for the PHY number 1. base is tse_mac_base, as you guessed, and data is the MDIO address.

Then you can access the register with one of those calls:

IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num)
IOWR_ALTERA_TSEMAC_MDIO(base, mdio, reg_num, data)

The first line reads, the second writes. base is again tse_mac_base, mdio is the PHY number (0 or 1, depending on the call you used to set up the MDIO address), reg_num the MDIO register number, and data is the value to write.

That's very nice.

i think that i have access through the mdio to the registers of PHY.

i also madethehardware reset for my phy and the led of phy blinks.

and is there any alghorithm of how to send\receive packets, how to config the descriptor to sgdma?

I don't use any Os.

I want to use functions of tse, sgdma to solve this problem.

besides i use functions from tse drivers of i don't know how to call it.

Hello to everybody i have another problem:

i took the example of sending of packet from tse driver, i also formed the descriptor for sgdma_tx, and try to send packet to PC.

Wireshark shows that packet with right number of bytes, but the packet is corrupted, besides all bytes of data are zero.

but i didn't configure the PHY.

I make lan adapter in PC to work in duplex 100 mbit and after hard reset PHY connects to it and by auto-negotiation works in duplex and 100 mbit - these parameters meet a demand of my fpga project.

then I form the packet as an example I took tse_mac_raw_send

Arу there any ideas why it doesn't work?

or where can i have a look for the control and status registers of PHY?

I use marvell 88e1111 and there is no datasheet for it.

can i take another datasheet to PHY with gigabit mode and look for the addresses of registers?

are there any standatrs for it?

thank for your help.

Not all registers are standard, unfortunately.

You can have a look at the TSE driver, it has a few lines configuring the Marvell PHY, you can re-use them in your project.

As for the empty data packet, it can come from the CPU data cache. Try to flush the data cache before sending the packet, or use the alt_remap_uncached() function to modify your pointer to the memory buffer that you fill in.

Hi Guys

I am new to FPGA world and pls correct me if I am wrong.

I brought Stratix II GX PCI development board and trying to compile and run TSE ref design as is. But getting following warnings and Quartus software is not generating any program files.

Warning: Can't generate programming files for project because design file "C:/altera/tse_datapath_reference_design/tse_ref_design/crcgen_altcrc.v" is encrypted. It does not have license file support that allows generation of programming files.

Warning: Can't generate programming files for project because design file "C:/altera/tse_datapath_reference_design/tse_ref_design/crcchk_altcrc.v" is encrypted. It does not have license file support that allows generation of programming files.

Any Help would be appreciated.