Forum Discussion
TSE MAC and Marvell 88E1111
I'm having trouble to bring up the TSE MAC to Ethernet interface on the Stratix II GX PCIe board. I was able to instantiate a triple speed Ethernet MAC and build logic around it. The loopback at the GMII interface seems work fine. However, I'm not able to send any packet out via the on board Marvell 88E1111 Ethernet transceiver. I suspect I need to program the registers in it via the MDIO. Is there a register map or data sheet of the 88E1111? Or is there anything else I'm missing?
Thanks.42 Replies
- Altera_Forum
Honored Contributor
Hi Foreshadow,
First of all look at your comand config register = 0x00000000 it can't be so in full duplex and 100 Mbit. Then the main error - no PHY, maybe there are some errors with physical connection of PHY. have a look in closed topics to this, there some pictures of pinouts, it should help you. - Altera_Forum
Honored Contributor
--- Quote Start --- Hi Foreshadow, First of all look at your comand config register = 0x00000000 it can't be so in full duplex and 100 Mbit. Then the main error - no PHY, maybe there are some errors with physical connection of PHY. have a look in closed topics to this, there some pictures of pinouts, it should help you. --- Quote End --- Thank you for your answer. I have found the solution here: http://www.alteraforum.com/forum/showthread.php?p=86569 И.. Кстати, из Ваших постов подчерпнул несколько весьма полезных замечаний, которые удалось применить в своем дизайне.. Спасибо))) А проблема была в том, что именно на этой отладочной плате (3sl150) неудачно подключен чип Marvell - нужно перезагружать вручную... - Altera_Forum
Honored Contributor
hi all
if you need, here is an interessant paper have fun and please, i need help for something, maybe some can help me on this forum : "Need help : implement Gigabit Ethernet" thanks in advance - Altera_Forum
Honored Contributor
I'm sorry but I had to edit your message and remove your attachment.
The datasheet is under an NDA and Marvell forbids anyone to reproduce it without their authorisation. I find it stupid but it's their rules ;) - Altera_Forum
Honored Contributor
ho i didn't know that
ty for the advice - Altera_Forum
Honored Contributor
can you please answer this simple question Marvel Alaska 88e1111 is software programmable? or hardware programmable only by changing low high states on its pin?
- Altera_Forum
Honored Contributor
--- Quote Start --- can you please answer this simple question Marvel Alaska 88e1111 is software programmable? or hardware programmable only by changing low high states on its pin? --- Quote End --- Hello, Marvell 88E1111 is a software programmable. Good Luck - Altera_Forum
Honored Contributor
Ok
I will try to give you an advice - Altera_Forum
Honored Contributor
--- Quote Start --- The TSE is able to communicate with up to two PHYs through MDIO. You need first to set up the MDIO address of the PHY, with one of those calls:
Obviously the first line sets the MDIO address for the PHY number 0 and the second one sets the MDIO address for the PHY number 1. base is tse_mac_base, as you guessed, and data is the MDIO address. Then you can access the register with one of those calls:IOWR_ALTERA_TSEMAC_MDIO_ADDR0(base,data) IOWR_ALTERA_TSEMAC_MDIO_ADDR1(base,data)
The first line reads, the second writes. base is again tse_mac_base, mdio is the PHY number (0 or 1, depending on the call you used to set up the MDIO address), reg_num the MDIO register number, and data is the value to write. --- Quote End --- Hi, I'd like to connect one TSE with two Marvell PHYs: 1- Are the above Macros are all that we need? 2- How we are going to connect the MDIO & MDC to both PHY devices? Your prompt response is highly appreciated. Thanks & Regards.IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num) IOWR_ALTERA_TSEMAC_MDIO(base, mdio, reg_num, data) - Altera_Forum
Honored Contributor
the MDIO is a shared bus. You can have a signgle MDC and a single MDIO pin on the FPGA, connected to both MDC and MDIO pins on the PHY chips.
If they are already connected separately, then you'll have to write a little logic to merge them into a single bus inside the FPGA. The MDC is output only so you can just duplicate the signal. The MDIO is bidirectionnal though, so you need a bit more. When used as an output you can duplicate it to both PHYs too, and when used as an input, just do an AND between the two inputs from the PHYs before feeding it to the TSE.