Trouble with Arria10 dev kit FPGA EMIF

It doesn’t seem that a pin_assignments.tcl script was generated, but since I’m implementing my project on the dev board, I had already copied and pasted the assignments in the qsf file. I double checked those and they seem to match. Where is that tcl script supposed to end up anyway?

I found that I had an extra sdc file in my project (from one of my earlier gyrations). Once I pulled that out I no longer had the constraint warnings. However, the emif still didn’t work. I added Signaltap to view some of the signals and saw that the local_cal_success signal wasn’t going high. There were no warning that I could see that lead to a solution though. Finally, I noticed that there were emif directories left over from my previous tries (same ip directories with a different unique value suffix). I deleted all of those, and recompiled. The compile took ~3 times longer, but now it’s working. I guess Quartus was running all of the tcl scripts that it could find and was plowing over the top of itself? I don’t know, but I’m on to the next hurdle!

Thanks for your time and advice!