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Honored Contributor
Honored ContributorTrouble with Arria10 dev kit FPGA EMIF
I’m having trouble implementing an FPGA DDR4 EMIF on the Altera Arria10 Dev board. I can generate the emif example design (with the traffic generator etc) and that works fine. But when I try to i...
Altera_ForumHonored Contributor
Honored ContributorWhile you don't have to run a pin_assignments.tcl script with Arria 10, you still have to make pin location assignments. Have you done that? The pin_assignments.tcl script is used to specify I/O related assignments, like voltage, drive strength, etc. The message you mention just indicates that with Arria 10, you don't have to run the script (while with older families, you still do). If you generated the example design for that specific dev kit, the pin location assignments were probably set for you. For your own project, you'd have to set them.
If you're using Quartus Pro, you can use BluePrint (now known as Interface Planner) to set up the I/O. Otherwise, you have to manually create location assignments in the Pin Planner or Assignment Editor. What "constraint warnings" are you getting?
