Trouble Update Partitioning in Device Tree
Hi,
I'm try startup Arrow SoCKit evalBoard include CycloneV, used guide "GSRD v13.1 - Booting from QSPI" from rocketboards.org, (https://rocketboards.org/foswiki/Documentation/GSRD131QspiBoot#A._Configure_Preloader_to_Boot_from_QSPI)
I'm use Ububtu12.04, Quartus 13.1, SoCEDS13.1 and "cv_soc_devkit_ghrd" folder from "quartus/embedded/examples"
In the step "D" need Edit the file cv_soc_devkit_ghrd/soc_system_board_info.xml: as stated in instruction. But after generation DTB files and replaced it on the SD-MMC card, kernel not started.
I tried to solve this problem by analyzing the source files DTS, using the working version of the DTS file from the original image of SD-MMC.
I managed to get it to boot up to the command line, but I don't see my expected partitioning:
step "E", point 3:
Boot Linux and run the following command to verify that the QSPI partitioning is correct:
# cat /proc/mtd
however, this command returns nothing to me:
root@socfpga_cyclone5:~# cat /proc/mtd
dev: size erasesize name
root@socfpga_cyclone5:~#
which says my partitioniing is not applied
I do everything according to the instructions, but I cannot understand why it does not work. I will be grateful for any help
ps:
source file DTS:
spi@ff705000 {
compatible = "cadence,qspi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xff705000 0x1000 0xffa00000 0x1000>;
interrupts = <0x0 0x97 0x4>;
master-ref-clk = <0x17d78400>;
ext-decoder = <0x0>;
num-chipselect = <0x4>;
fifo-depth = <0x80>;
bus-num = <0x2>;
n25q128@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "n25q128";
reg = <0x0>;
spi-max-frequency = <0x5f5e100>;
page-size = <0x100>;
block-size = <0x10>;
quad = <0x1>;
tshsl-ns = <0xc8>;
tsd2d-ns = <0xff>;
tchsh-ns = <0x14>;
tslch-ns = <0x14>;
partition@0 {
label = "Flash 0 Raw Data";
reg = <0x0 0x800000>;
};
partition@800000 {
label = "Flash 0 jffs2 Filesystem";
reg = <0x800000 0x800000>;
};
};
n25q128@1 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "n25q128";
reg = <0x1>;
spi-max-frequency = <0x5f5e100>;
page-size = <0x100>;
block-size = <0x10>;
quad = <0x1>;
tshsl-ns = <0xc8>;
tsd2d-ns = <0xff>;
tchsh-ns = <0x14>;
tslch-ns = <0x14>;
partition@0 {
label = "Flash 1 User Data";
reg = <0x0 0x1000000>;
};
};
};
editing files i'm try use:
flash@0xff705000 {
compatible = "cadence,qspi-1.0", "cadence,qspi";
reg = <0xff705000 0x1000 0xffa00000 0x1000>;
reg-names = "axi_slave0", "axi_slave1";
interrupt-parent = <0x2>;
interrupts = <0x0 0x97 0x4>;
bus-num = <0x2>;
fifo-depth = <0x80>;
num-chipselect = <0x4>;
bank-width = <0x2>;
device-width = <0x1>;
master-ref-clk = <0x17d78400>;
ext-decoder = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
n25q00@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "n25q00";
reg = <0x0>;
spi-max-frequency = <0x5f5e100>;
page-size = <0x100>;
block-size = <0x10>;
m25p,fast-read;
read-delay = <0x4>;
tshsl-ns = <0x32>;
tsd2d-ns = <0x32>;
tchsh-ns = <0x4>;
tslch-ns = <0x4>;
partition@0 {
label = "Flash 0 Raw Data";
reg = <0x0 0x800000>;
};
partition@800000 {
label = "Flash 1 jffs2 Filesystem";
reg = <0x800000 0x1000000>;
};
partition@1800000 {
label = "FPGA Image";
reg = <0x1800000 0x800000>;
};
};
};