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maximilien_fpga's avatar
maximilien_fpga
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2 years ago

Triple Speed Ethernet Internal Loopback Error

Hello Everybody,

I come to you asking for help regarding an issue I have encountered whilst implementing the intel TSE IP in a project.

I am using a Cyclone 10 board.

I've instantiated the TSE IP as 10/100/100 MAC with RGMII connection and 2 internal FIFOs of size 2048x8. This IP is connected to two AvST interfaces. One is a DMA like device sending data to the transmit port whilst the receive is connected to a MSGDMA (I have verified that the ff_rx_rdy = '1').

The clock configuration of the TSE consists of two clocks for the time being, a 80 Mhz clock for the control port and a 125 Mhz clock connected to the following ports:

-pcs_mac_tx_clock

-pcs_mac_rx_clock

-receive_clock

-transmit_clock

The IP configuration is set_1000 = '1' whilst other signals are low or open. I do not need to use 10/100 Mbs eth speeds only 1Gb.

Regarding the CSR I have followed the recommendations of the Intel user guide.

Screenshots of the top_level file, the C initialization and my Qsys will be linked below.

The issue that I have encountered is that when in internal loopback mode, the IP data is sent onto the AvST ff_tx but not seen on ff_rx. After having investigated this with signal tap for a rather long time I believe the issue is that the data is shifted over by 1 byte in the LBFF (loopback fifo), image is provided below.

Anyone experienced this issue before or have an idea on how to resolve it?

I would very much appreciate your feedback.

Kind Regards

Maximilien

7 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi，

    ​

    Thanks for submitting the issue.

    Please do allow me have some time to look into the issue and I will get back to you with findings.


    Best regards,

    Zi Ying


    • maximilien_fpga's avatar
      maximilien_fpga
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hello Zi Ying,

      Just to update you I have recovered the Avalon stream but still get a shift in the Loopback FIFO even though RX clock and TX clock are the same (which is the recommended configuration in the Intel user guide).

      Do you have any idea what may cause this shift, if it is not the TX/RX clock relation?

      Kind Regards

      Maximilien

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Maximilien,


    May I know that you are using which Quartus version?


    Best regards,

    Zi Ying


  • maximilien_fpga's avatar
    maximilien_fpga
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello Zi Ying,

    I am currently using Quartus Prime Version 20.1.1 and a Intel Cyclone 10LP FPGA.

    This model should be clear of architectural GPIO issues preventing it from closing timing.

    Additionally do you know if the new Agilex family will be compatible with this IP and RGMII?

    Let me know if you have any other insights on what may cause the issue I have with this MAC loopback as this link you've provided does not concern the chip I am currently using.

    Kind Regards

    Maximilien

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Maximilien,


    Since no hear any feedback from you, I am now close the case.

    If you have any question after the case closed, please do feel free to submit another issue.


    Best regards,

    Zi Ying