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maximilien_fpga's avatar
maximilien_fpga
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2 years ago

Triple Speed Ethernet Internal Loopback Error

Hello Everybody, I come to you asking for help regarding an issue I have encountered whilst implementing the intel TSE IP in a project. I am using a Cyclone 10 board. I've instantiated the TSE ...
ZiYing_Intel's avatar
ZiYing_Intel
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2 years ago

Hi，

​

Thanks for submitting the issue.

Please do allow me have some time to look into the issue and I will get back to you with findings.


Best regards,

Zi Ying


  • maximilien_fpga's avatar
    maximilien_fpga
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    2 years ago

    Hello Zi Ying,

    Just to update you I have recovered the Avalon stream but still get a shift in the Loopback FIFO even though RX clock and TX clock are the same (which is the recommended configuration in the Intel user guide).

    Do you have any idea what may cause this shift, if it is not the TX/RX clock relation?

    Kind Regards

    Maximilien