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JhonatanRubin's avatar
JhonatanRubin
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6 years ago

Tri Speed ETH MAC - MAX10

Hi all, We are using CAST UDP IP core on MAX 10, as part of the design it uses the TriSpeed ETH MAC, the final HW design is fimiliar to the MAX10 EVB (10M50DAF484C6GES with RGMII to Marvell 88e1111) ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

This may be due to the IO buffer performance instead of related TSE IP related. It is expected that the 3.3V IO performance is lower than the 2.5V as the 3.3V is a target for low-speed application with the wide threshold requirement but causing a slow rise/hold time. Also, did you change the VCCIO on board when you switch the IO from 2.5 to 3.3V? This also might impact the IO behavior.

Regards -SK


  • JhonatanRubin's avatar
    JhonatanRubin
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi SengKok_L_Intel Thank you very much for the replay, I always use the same IO standard as connected to the Vccio, therfore when i used the bank as a 3.3V it is because the Vccio is 3.3V, is it possible to connect a 3.3V rail to the Vccio and a 2.5V IO stadnard? As for the differences between the IO performance, i didnt found any documentation that state what you are saying, the only thing i found is a "high speed" decleration regardless of what Voltage is used, can you refer any documentation that backs up the performance differences according to the IO stadnard? Thanks Jhonatan

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