Dear Sam,
As I understand it, you have some inquiries related to the QSFP refclk for the S10 H-tile devkit which is running at 644.53125MHz by default. You would like run the refclk at 320MHz. Please correct me if I am wrong, I believe you are referring to the REFCLK_QSFPI1 (644.53125 MHz LVDS) which is the OUT1 of Si5341A. If yes, for your information, you may try to use the Clock Controller to change it to other frequency that you are targeting. You may refer to "Clock Controller" section and "Figure 32. Clock Controller - Si5341" in the Intel® Stratix® 10 GX FPGA Development Kit User Guide for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Occasional Contributor
