Forum Discussion
Hi MaheshRV,
Do you still require help for this issue?
Can try the below:
- Run the "- profile" as "-profile"
- Compile whitout a the "-profile"
Thanks.
Regards,
Aik Eu
- MaheshRV4 years ago
New Contributor
Yes, we still need help here as we are still facing the same issue.
Regarding "Run the "- profile" as "-profile" " , yes we had already tried with "-profile" the space in the query got added by mistake.
Regarding "Compile whitout a the "-profile" " , yes, we have compiled without the "-profile" itself.
Even after this, we are still seeing the issue.
Further to add, what we observe is-
We are able to run -profile with less (PE = 32, 64) configuration but when we are increasing our configuration (PE = 128/256) the resources utilized are exceeding the FPGA size.
Is there any way to optimize the profile logic so that we can fit in the given FPGA. Using Stratix 10MX where 80% is utilized by our code (with maximum config).
- aikeu4 years ago
Regular Contributor
Hi MaheshRV,
May I know the your openCL version?
Other than that, where do you specify your PE configuration value?
Thanks.
Regards,
Aik Eu
- MaheshRV4 years ago
New Contributor
Regarding
- "May I know the your openCL version?"
The openCL version we are using is 21.1
Regarding
- "Other than that, where do you specify your PE configuration value?"
The PE configuration value is defined in the file “opencl_defines.h” as a macro/fixed value. Hence, If we want to change the PE value, we modify this macro and again we need to recompile and generate the “.aocx” file.