Toggling HSMC GPIO as IO pins

Yes you can. You may need to check the schematic to identify which MAX 10 FPGA pin is connecting to HSMC GPIO IO pin, then toggle that with your design in Quartus.

Okay, Thanks for the response

As I'm trying the same where input clock is assign for two output signal(q1, q2)

One is q1 rooted to HSMC GPIO, another is q2 rooted to PMODA

Here q2 signal I can see the output pulse of clock through oscilloscope

Where q1 signal which is of HSMC GPIO pin assigned...I didn't get the pulse. Whether am I missing something to check the output correctly?

q1 <= clk; -- pin planner y7

q2 <= clk; -- pin planner c7 (for reference)

Please find the attachment of workspace, kindly acknowledge the response

Thanks & Regards,

Kothapalli Dora Sai Manikanta

Can you try on the other pin HSMC GPIO pin? Also, check or probe the CLK pin and see whether it has output?

yes, I tried probing the CLK pin to another HSMC GPIO pin, I can't see CLK pulse in another pin too...!

I think you have to connect correctly all the input and output to guarantee the function. Please take a look at the user guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf#page=52