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Altera_Forum
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15 years ago

Timing violation TRDB_D5M_CD_v1.0 and DE_TV demos

Hello

I has create a symbol with the toplevel from the 5 megapixel demo project TRDB_D5M_CD_v1.0 for DE2 Board.

But when I insert the symbol in a block diagram and sets the Input/Output, after the synthese I have timing violation and the VGA-Monitor d'ont display a perfect image.

The same problem I have with the video demo on the Terasic CD DE2_TV.

In the attachment you find the two demo project, could you try on your system? Maybe your found the problem....

For any tips I thanks....

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I am having similar problems, the design compiles but fails several timing analysis tests. Has anyone solved these problems?