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Altera_Forum
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16 years ago

Timing violation TRDB_D5M_CD_v1.0 and DE_TV demos

Hello I has create a symbol with the toplevel from the 5 megapixel demo project TRDB_D5M_CD_v1.0 for DE2 Board. But when I insert the symbol in a block diagram and sets the Input/Output, af...
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Altera_Forum
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15 years ago

I am having similar problems, the design compiles but fails several timing analysis tests. Has anyone solved these problems?