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fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Fred,

Do you have any other questions or help needed?

Thanks.

-YY

fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hi YY, Oh, I think I might change design architecture to solve this unstable issue in the FPFA if you cannot find a solution in the device side, but I need to do some experiments in the next week to confirm what I thought since I need to solve more important issue in another topic during this design. If you would like to close this case, please do it. Again thank so much for your support😊 Thanks, -Fred

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